High speed computer systems and, in particular, those referred to as "main-frame" systems typically employ cache memories as integral parts of their overall system architectures. Cache memories are typically low capacity data storage devices that are particularly optimized for high speed data access. One or more cache memories are typically closely coupled to each respective central processing unit (CPU) of the system to permit extremely high rates of data exchange. Conversely, the mainstore is a relatively low access speed, high capacity optimized storage unit utilized in common by all of the CPUs of the system. This implies the further requirement of a mainstore access prioritization and arbitration mechanism that, by its operation, may further adversely impact the required length of time for accessing mainstore. The data processing through-put of each CPU is thus greatly enhanced whenever its memory requirements can be met by accessing its closely associated, or local, cache memory. Generally, all other memory requests, i.e., those that cannot be satisfied from a local cache memory, must be satisfied by accessing the much slower mainstore memory unit.
Conventionally, operation of the CPU generally involves requests for two basic types of mainstore memory accesses. The first type is a fetch, or move-in, of program instructions and data or, generically, just data. The second is to store, or move-out, potentially modified data. The move-in of data from mainstore in response to a CPU request is typically treated as a high priority function within the data processing system. This assignment of priority is to ensure that the immediate data requirements of the CPU are kept current. Typically with the move-in of data, a data copy is kept in a local cache memory of the requesting CPU. Significantly, there is a substantial likelihood of the CPU again requesting these most recently moved-in data, hence the value of cache memories.
When the cache memory is full and a move-in request must be satisfied from mainstore, at least a corresponding amount of cache memory space must be first freed by the prior performance of a data move-out operation to the mainstore memory unit. Since conventional mainstore memory units are primarily optimized for storage capacity while cache buffers are highly optimized for speed, special memory access functions are not available. That is, without dual independent read/write port memory capability in both the cache buffers and mainstore memory unit, a simultaneous move-in and move-out of data cannot be accomplished. Thus, execution of a data move-out must be completed before beginning the move-in of data, so as to free adequate memory space within the cache buffer. Typically, a simple data latch is utilized to temporarily store the move-out data without requiring a mainstore memory access. This allows the move-in of data to proceed without significant delay. However, the move-out data must then be immediately written to mainstore upon completion of the move-in mainstore access. Otherwise, the move-out data will be held inaccessible to all CPUs until it is finally written out. Further, while it is so held in the temporary latch, it must be protected from being overwritten and, therefore, will block any subsequent move-in request requiring a prior cache buffer data move-out. The overall operating performance of the data processing system is, consequently, significantly degraded by the required performance of a data move-out either before or immediately after the satisfaction of each move-in request when the cache memory of the requesting CPU is full at the moment of the request.
A pervasive problem associated with the above mainstore access contention problem, and the use of cache memory subsystems in general, is the requirement for providing system-wide data integrity. The copying of data into even the first of potentially multiple cache memories means that multiple alterable copies could be present within the data processing system. Thus, a mechanism within the architecture of the data processing system is required to ensure that only the most current copy of any particular data is provided in response to any request for a data copy in alterable form. A variety of such mechanisms, or data integrity schemes, are known. Typically, a data integrity bit field, within an address tag, is associated with each unit of data present outside of mainstore. The bit subfields of a tag typically reference the system address of the data and indicate whether the present copy of the data may be modified. However, significant with respect to the present invention, all modifications and enhancements of a cache based system architecture are substantially complicated by the requirement of supporting whatever data integrity mechanism is in use.